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White Electronic Designs
W3EG64128S-AD4 -BD4
PRELIMINARY*
1GB - 2x64Mx64 DDR SDRAM UNBUFFERED w/PLL
FEATURES
Double-data-rate architecture Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Dual Rank Power supply: 2.5V 0.2V JEDEC standard 200 pin SO-DIMM package * Package height options: BD4: 31.75 mm (1.25")
* This product is under development, is not qualified or characterized and is subject to change without notice.
DESCRIPTION
The W3EG64128S is a 2x64Mx64 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM component. The module consists of eight 128Mx8 stack DDR SDRAMs in 66 pin TSOP packages mounted on a 200 pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
NOTE: Consult factory for availability of: * RoHS compliant products * Vendor source control options * Industrial temperature option
OPERATING FREQUENCIES
DDR333 @CL=2.5 Clock Speed CL-tRCD-tRP 166MHz 2.5-3-3 DDR266 @CL=2 133MHz 2-2-2 DDR266 @CL=2.5 133MHz 2.5-3-3 DDR200 @CL=2 100MHz 2-2-2
May 2004 Rev. 0
1
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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PIN CONFIGURATION
PIN# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
May 2004 Rev. 0
W3EG64128S-AD4 -BD4
PRELIMINARY
PIN NAMES
SYMBOL DQ42 DQ46 DQ43 DQ47 VCC VCC VCC NC VSS NC VSS VSS DQ48 DQ52 DQ49 DQ53 VCC VCC DQS6 DQM6 DQ50 DQ54 VSS VSS DQ51 DQ55 DQ56 DQ60 VCC VCC DQ57 DQ61 DQS7 DQM7 VSS VSS DQ58 DQ62 DQ59 DQ63 VCC VCC SDA SA0 SCL SA1 VCCSPD SA2 VCCID NC
2
SYMBOL PIN# VREF 51 VREF 52 53 VSS VSS 54 DQ0 55 DQ4 56 DQ1 57 DQ5 58 VCC 59 VCC 60 DQS0 61 DQM0 62 DQ2 63 DQ6 64 65 VSS VSS 66 DQ3 67 DQ7 68 DQ8 69 DQ12 70 VCC 71 72 VCC DQ9 73 DQ13 74 DQS1 75 DM1 76 VSS 77 78 VSS DQ10 79 DQ14 80 DQ11 81 DQ15 82 VCC 83 VCC 84 CK0 85 VCC 86 CK0# 87 88 VSS VSS 89 VSS 90 DQ16 91 DQ20 92 DQ17 93 DQ21 94 VCC 95 96 VCC DQS2 97 DQM2 98 DQ18 99 DQ22 100
SYMBOL PIN# VSS 101 VSS 102 DQ19 103 DQ23 104 DQ24 105 DQ28 106 VCC 107 VCC 108 DQ25 109 DQ29 110 DQS3 111 DQM3 112 VSS 113 VSS 114 DQ26 115 DQ30 116 DQ27 117 DQ31 118 VCC 119 VCC 120 CB0 121 CB4 122 CB1 123 CB5 124 VSS 125 VSS 126 DQS8 127 DQM8 128 CB2 129 CB6 130 VCC 131 VCC 132 CB3 133 CB7 134 NC 135 NC 136 VSS 137 VSS 138 NC 139 VSS 140 NC 141 VCC 142 VCC 143 VCC 144 NC 145 CKE0 146 NC 147 NC 148 A12 149 A11 150
SYMBOL PIN# A9 151 A8 152 VSS 153 VSS 154 A7 155 A6 156 A5 157 A4 158 A3 159 A2 160 A1 161 A0 162 VCC 163 VCC 164 A10/AP 165 BA1 166 BA0 167 RAS# 168 WE# 169 CAS# 170 CS0 171 NC 172 NC 173 NC 174 VSS 175 VSS 176 DQ32 177 DQ36 178 DQ33 179 DQ37 180 VCC 181 VCC 182 DQS4 183 DQM4 184 DQ34 185 DQ38 186 VSS 187 VSS 188 DQ35 189 DQ39 190 DQ40 191 DQ44 192 VCC 193 VCC 194 DQ41 195 DQ45 196 DQS5 197 DQM5 198 VSS 199 VSS 200
A0-A12 BA0-BA1 DQ0-DQ63 CB0-CB7 DQS0-DQS8 CK0 CK0# CKE0 CS0# RAS# CAS# WE# DQM0-DQM8 VCC VCCQ VSS VREF VCCSPD SDA SCL SA0-SA2 VCCID NC
Address input (Multiplexed) Bank Select Address Data Input/Output Ckeck bits Data Strobe Input/Output Clock Input Clock Input Clock Enable input Chip Select Input Row Address Strobe Column Address Strobe Write Enable Data-In Mask Power Supply (2.5V) Power Supply for DQS (2.5V) Ground Power Supply for Reference Serial EEPROM Power Supply (2.3V to 3.6V) Serial data I/O Serial clock Address in EEPROM VCC Indentification Flag No Connect
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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FUNCTIONAL BLOCK DIAGRAM
W3EG64128S-AD4 -BD4
PRELIMINARY
CS1# CS0# DQS0 DQM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CS# DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DQM7 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS CS# CS# DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DQM6 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS CS# CS# DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DQM5 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS CS# DQS4 DQM4 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS
CS#
CS#
U1
U5
U2
U6
U3
U7
U4
U8
VCC CK0 CKDA
CLK0/CLK0# CLK1/CLK1#
PLL
CK0# CKDA#
CLK2/CLK2# CLK3/CLK3#
FEEDBACK RAS# CAS# BA0-BA1 WE# A0-A12 CKE0 CKE1 RAS: SDRAMs U1-U8 CAS: SDRAMs U1-U8 BA0-BA1: SDRAMs U1-U8 SERIAL PD WE: SDRAMs U1-U8 A0-A12: SDRAMs U1-U8 SA0 CKE0: SDRAMs U1-U8 CKE1: SDRAMs U1-U8 VCC NOTE: All datalines are terminated through a 22 ohm series resistor GND U1-U8 U1-U8 SA1 SA2 SCL A0 A1 A2 SDA
May 2004 Rev. 0
3
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ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Current
Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
W3EG64128S-AD4 -BD4
PRELIMINARY
Symbol VIN, VOUT VCC, VCCQ TSTG PD IOS
Value -0.5 ~ 3.6 -1.0 ~ 3.6 -55 ~ +150 9 50
Units V V C W mA
DC CHARACTERISTICS
0c TA 70C, VCC = 2.5V 0.2V Parameter Supply Voltage Supply Voltage Reference Voltage Termination Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Symbol VCC VCCQ VREF VTT VIH VIL VOH VOL Min 2.3 2.3 1.15 1.15 VREF+0.15 -0.3 VTT+0.76 -- Max 2.7 2.7 1.35 1.35 VDDQ+0.3 VREF-0.15 -- VTT-0.76 Unit V V V V V V V V
CAPACITANCE
TA = 23C, f = 1MHz, VCC = 3.3V, VREF = 1.4V 200mV
Parameter Input Capacitance (A0-A12) Input Capacitance (RAS#, CAS#, WE#) Input Capacitance (CKE0, CKE1) Input Capacitance (CK0, CK0#) Input Capacitance (CS0#, CS1#) Input Capacitance (DQM0-DQM8) Input Capacitance (BA0-BA1) Data input/output capacitance (DQ0-DQ63)(DQS) Data input/output capacitance (CB0-CB7)
May 2004 Rev. 0 4
Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 COUT COUT
Max 53 53 53 5.5 53 8 53 8 8
Unit pF pF pF pF pF pF pF pF pF
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W3EG64128S-AD4 -BD4
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0c TA 70C, VCCQ = 2.5V 0.2V, VCC = 2.5V 0.2V Parameter Symbol Conditions One device bank; Active - Precharge; tRC=tRC(MIN); tCK=tCK(MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. One device bank; Active-Read-Precharge; Burst = 2; tRC=tRC(MIN);tCK=tCK(MIN); Iout = 0mA; Address and control inputs changing once per clock cycle. All device banks idle; Power- down mode; tCK=tCK(MIN); CKE=(low) CS# = High; All device banks idle; tCK=tCK(MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. One device bank active; Power-down mode; tCK(MIN); CKE=(low) CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS(MAX); tCK=tCK(MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. Burst = 2; Reads; Continous burst; One device bank active;Address and control inputs changing once per clock cycle; tCK=tCK(MIN); Iout = 0mA. Burst = 2; Writes; Continous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK(MIN); DQ,DM and DQS inputs changing twice per clock cycle. tRC=tRC(MIN) CKE 0.2V Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK(MIN); Address and control inputs change only during Active Read or Write commands. DDR333@CL=2.5 Max DDR266@CL=2.5 Max DDR200@CL=2 Max Units
Operating Current
IDD0
2915
2915
2915
mA
Operating Current
IDD1
3315
3315
3315
mA
Precharge Power-Down Standby Current
IDD2P
96
96
96
mA
Idle Standby Current
IDD2F
1075
1075
1075
mA
Active Power-Down Standby Current
IDD3P
800
800
800
mA
Active Standby Current
IDD3N
1795
1795
1795
mA
Operating Current
IDD4R
3795
3795
3795
mA
Operating Current
IDD4W
4275
4275
4275
mA
Auto Refresh Current Self Refresh Current
IDD5 IDD6
5235 355
5235 355
5235 355
mA mA
Operating Current
IDD7A
7955
7955
7955
mA
May 2004 Rev. 0
5
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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W3EG64128S-AD4 -BD4
PRELIMINARY
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1 : OPERATING CURRENT : ONE BANK
1. 2. 3. Typical Case : VCC=2.5V, T=25C Worst Case : VCC=2.7V, T=10C Only one bank is accessed with tRC (min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. IOUT = 0mA Timing Patterns : * DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRCD=2*tCK, tRAS=5*tCK Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4, tRCD=10*tCK, tRAS=7*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst
IDD7A : OPERATING CURRENT : FOUR BANKS
1. 2. 3. Typical Case : VCC=2.5V, T=25C Worst Case : VCC=2.7V, T=10C Four banks are being interleaved with tRC (min), Burst Mode, Address and Control inputs on NOP edge are not changing. Iout=0mA Timing Patterns : * DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2, BL=4, tRRD=2*tCK, tRCD=2*tCK Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst
4.
4.
*
*
*
*
*
*
Legend : A = Activate, R = Read, W = Write, P = Precharge, N = NOP A (0-3) = Activate Bank 0-3 R (0-3) = Read Bank 0-3
May 2004 Rev. 0
6
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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ORDERING INFORMATION FOR AD4
Part Number W3EG64128S335AD4 W3EG64128S262AD4 W3EG64128S265AD4 W3EG64128S202AD4 Speed 166MHz/333Mb/s 133MHz/266Mb/s 133MHz/266Mb/s 100MHz/200Mb/s CAS Latency 2.5 2 2.5 2 tRCD 3 2 3 2
W3EG64128S-AD4 -BD4
PRELIMINARY
tRP 3 2 3 2
Height* 35.05 (1.38") 35.05 (1.38") 35.05 (1.38") 35.05 (1.38")
NOTES: * Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) * Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option
PACKAGE DIMENSIONS FOR AD4
67.56 (2.66) MAX. 2.0 (0.079)
3.81 (0 .150) MAX.
3.98 0.1 (0.157 0.004) 20 (0.787)
35.05 (1.38) MAX.
P1
2.31 (0.091) REF.
4.19 (0.165) 1.80 (0.071) 11.40 (0.449)
47.40 (1.866)
3.98 (0.157) MIN. 1.0 0.1 (0.039 0.004)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
May 2004 Rev. 0
7
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
ORDERING INFORMATION FOR BD4
Part Number W3EG64128S335BD4 W3EG64128S262BD4 W3EG64128S265BD4 W3EG64128S202BD4 Speed 166MHz/333Mb/s 133MHz/266Mb/s 133MHz/266Mb/s 100MHz/200Mb/s CAS Latency 2.5 2 2.5 2 tRCD 3 2 3 2
W3EG64128S-AD4 -BD4
PRELIMINARY
tRP 3 2 3 2
Height* 31.75 (1.25") 31.75 (1.25") 31.75 (1.25") 31.75 (1.25")
NOTES: * Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) * Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option
PACKAGE DIMENSIONS FOR BD4
67.56 (2.666) MAX
C27 R17 R5 R18 R19 R20 R9 R2 R11 R12 R10 R13
3.81 (0.150) MAX.
R7
R16
R15
3.98 0.1 (0.157 0.004)
R6
U1
C28 R3
R14
U3
U5
U7
U9
31.75 (1.25) 20 (0.787)
R8
R4
C29 C3 RP1 RP5 RP9 C5 RP14 C2 RP18 RP13 RP19 C3
R21 C6 RP4 RP7 C18 RP12 C7 RP20 RP22 C8 C26
2.31 (0.091) REF.
4.19 (0.165) 1.80 (0.071)
47.40 (1.866)
3.98 (0.157) MIN. 1.0 0.1 (0.039 0.004)
11.40 (0.449)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
May 2004 Rev. 0
8
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
Document Title
1GB - 2x64Mx64 DDR SDRAM UNBUFFERED w/PLL
W3EG64128S-AD4 -BD4
PRELIMINARY
Revision History Rev #
Rev 0 Rev 1
History
Initial Release 1.1 Update to capacitance and IDD data 1.2 Added test conditions data 1.3 Added BD4 package option
Release Date
7-17-03 4-1-04
Status
Advanced Preliminary
May 2004 Rev. 0
9
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com

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